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III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-7
A-1
B-III
SIF
Control and Operation of Clock-Synchronized Transfer
Transmit control
(1) Enabling transmit operation
Use the transmit-enable bit TXENx for transmit control.
Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401F8)
When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for
input), thus allowing for data to be transmitted. The synchronizing clock input/output of the #SCLKx pin is
also enabled (ready for input/output).
Transmit is disabled by writing "0" to TXENx.
After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK
pins are changed at follows:
#SRDY: When slave mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
#SCLK: When master mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so
the communication mode is half-duplex. Therefore, TXENx and receive-enable bit RXENx cannot
be enabled simultaneously. When transmitting data, fix RXENx at "0" and do not change it during
a transmit operation.
In addition, make sure TXENx is not set to "0" during a transmit operation.
(2) Transmit procedure
The serial interface contains a transmit shift register and a transmit data register (transmit data buffer), which
are provided independently of those used for a receive operation.
Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
The serial interface contains a status bit to indicate the status of the transmit data register.
Ch.0 transmit data buffer empty: TDBE0 (D1) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit data buffer empty: TDBE1 (D1) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit data buffer empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit data buffer empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7)
This bit is reset to "0" by writing data to the transmit-data register, and set to "1" again (buffer empty) when
the data is transferred to the shift register.
The serial interface starts transmitting when data is written to the transmit data register.
The transfer status can be checked using the transmit-completion flag (TENDx).
Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7)
This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all
data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure
8.5).
Following explains transmit operation in both the master and slave modes.