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II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-2 EPSON S1C33L03 FUNCTION PART
Contents of table
"Hex No." indicates an interrupt number in hexadecimal value.
"Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an
offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table
by default is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR
register (0x48134 to 0x48137).
For details about the trap table contents including exception factors, etc., refer to the "S1C33000 Core CPU
Manual".
"Interrupt system (Peripheral circuit)" indicates that interrupt levels can be programmed for each peripheral
circuit written.
"Interrupt factor" indicates the factor of the interrupt occurring in each interrupt system.
"IDMA Ch." indicates that an interrupt factor which has a numeric value in this column can start up the
intelligent DMA (IDMA) to transfer data when an interrupt factor occurs. The numeric value indicates the
IDMA's channel number. Interrupt factors that do not have a numeric value here cannot start up the IDMA.
"Priority" indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt
level. If two or more interrupt factors occur simultaneously, interrupt requests are accepted in order of highest
priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the
priorities of interrupt factors in the same interrupt system are fixed in the order that they are written here.
Maskable interrupt generating conditions
A maskable interrupt to the CPU occurs when all of the conditions described below are met.
•The interrupt enable register for the interrupt factor that has occurred is set to "1".
•The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to "1".
•The interrupt factor that has occurred has a higher priority level than the value that is set in the PSR's
Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt
system.)
•No other trap factor having higher priority, such as NMI, has occurred.
•The interrupt factor does not invoke IDMA (the IDMA request bit is set to "0").
When an interrupt factor occurs, the corresponding interrupt factor flag is set to "1" and the flag remains set
until it is reset in the software program. Therefore, in no cases can the generated interrupt factor be
inadvertently cleared even if the above conditions are not met when the interrupt factor has occurred. The
interrupt will occur when the above conditions are met.
However, when the interrupt factor invokes IDMA, the interrupt factor is reset if the following condition is
met.
•The IDMA transfer counter is not "0".
•Interrupts are disabled in the IDMA control information even if the transfer counter is "0".
If two or more maskable interrupt factors occur simultaneously, the interrupt factor that has the highest
priority is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept
pending until the above conditions are met.
The PSR and interrupt control register will be detailed later.
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in
this manual.