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V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-5
A-1
B-V
HSDMA
D0ADRL[15:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228)
D1ADRL[15:0]: Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238)
D2ADRL[15:0]: Ch. 2 destination address [15:0] (D[F:0]) / Ch. 2 low-order destination address set-up register (0x48248)
D3ADRL[15:0]: Ch. 3 destination address [15:0] (D[F:0]) / Ch. 3 low-order destination address set-up register (0x48258)
D0ADRH[11:0]: Ch. 0 destination address [27:16] (D[B:0]) / Ch. 0 high-order destination address set-up register (0x4822A)
D1ADRH[11:0]: Ch. 1 destination address [27:16] (D[B:0]) / Ch. 1 high-order destination address set-up register (0x4823A)
D2ADRH[11:0]: Ch. 2 destination address [27:16] (D[B:0]) / Ch. 2 high-order destination address set-up register (0x4824A)
D3ADRH[11:0]: Ch. 3 destination address [27:16] (D[B:0]) / Ch. 3 high-order destination address set-up register (0x4825A)
Address increment/decrement control
The source and/or destination addresses can be incremented or decremented when one data transfer is
completed. The SxIN[1:0] bits (for source address) and DxIN[1:0] bits (for destination address) are used to
set this function.
S0IN[1:0]:
Ch. 0 source address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226)
S1IN[1:0]: Ch. 1 source address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236)
S2IN[1:0]: Ch. 2 source address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246)
S3IN[1:0]: Ch. 3 source address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256)
D0IN[1:0]: Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A)
D1IN[1:0]: Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A)
D2IN[1:0]: Ch. 2 destination address control (D[D:C]) / Ch. 2 high-order destination address set-up register (0x4824A)
D3IN[1:0]: Ch. 3 destination address control (D[D:C]) / Ch. 3 high-order destination address set-up register (0x4825A)
SxIN/DxIN = "00": address fixed (default)
The address is not changed by a data transfer performed. Even when transferring multiple data, the transfer
data is always read/write from/to the same address.
SxIN/DxIN = "01": address decremented without initialization
The address is decremented by an amount equal to the data size set by DATSIZEx when one data transfer is
completed. The address that has been decremented during transfer does not return to the initial value.
SxIN/DxIN = "10": address incremented with initialization
If this function is selected in single and successive transfer modes, the address is incremented by an amount
equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been
incremented during transfer does not return to the initial value.
In block transfer mode too, the address is incremented when one data unit is transferred. However, the
address that has been incremented during a block transfer recycles returns to the initial value when the block
transfer is completed.
SxIN/DxIN = "11": address incremented without initialization
The address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is
completed. The address that has been incremented during transfer does not return to the initial value.