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VII LCD CONTROLLER BLOCK: LCD CONTROLLER
B-VII-2-6 EPSON S1C33L03 FUNCTION PART
Use the EDMAEN (D3)/LCDC system control register (0x39FFFD) to mask the #DMAREQx signals.
EDMAEN = "1": External DMA requests enabled
EDMAEN = "0": External DMA requests disabled (default)
Use the BREQEN (D2)/LCDC system control register (0x39FFFD) to mask the #BUSREQ signals.
BREQEN = "1": External bus release requests enabled
BREQEN = "0": External bus release requests disabled (default)
Other settings, such as memory specification-related settings, are made using the registers of the BCU and
SDRAM controllers. For details, refer to the description of the respective controllers.
LCD Controller Setting Procedure
Procedure to access the LCDC registers (when using #WAIT signal)
1. A6IO (D9)/access control register (0x48132) = "1"
This sets area 6 so that the internal device will be accessed.
2. A6WT[2:0] (D[A:8])/areas 6–4 setup register (0x4812A) = "000"
This sets area 6 so that it can be accessed with no wait states.
3. SWAITE (D0)/bus control register (0x4812E) = "1"
This enables the #WAIT signal.
4. The LCDC registers can be accessed.
Procedure to enable the LCD panel
1. SEMAS (D2)/bus control register (0x4812E) = "1"
This enables an external bus master.
2. LCDEN (D5)/LCDC mode register 2 (0x39FFE3) = "1"
This enables the LCD controller.
3. CFP3[5:4] (D[5:4])/P3 function select register (0x402DC) = "11"
This sets the P35 pin as the #BUSACK output and the P34 pin as the #BUSREQ input.
4. Initializing the LCDC registers
Setup the LCDC register as necessary except for the look-up table registers (0x39FFF5, 0x39FFF7) as
necessary.
5. LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) = "11"
This sets the LCD controller in power save mode to normal operation mode. Wait until the LCD
controller completes the power-up sequence.
6. Setting the look-up table
Setup the look-up table by writing data to the look-up table address register (0x39FFF5) and look-up table
data register (0x39FFF7).
Setting the number of wait states for accessing the LCDC registers (area 6) when
#WAIT signal is disabled
• The LCDC registers except for the look-up table data register (0x39FFF7) should be accessed with 4 wait
states inserted.
• When writing data to the look-up table data register (0x39FFF7), red and green data should be written
with 4 wait states inserted (1st and 2nd writes in a sequence), and blue data should be written with 7 wait
states inserted (last write in a sequence).
Use A6WT[2:0] (D[A:8])/areas 6–4 setup register (0x4812A) to set the number of wait states to be inserted
when area
6 is accessed.