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II CORE BLOCK: ITC (Interrupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-9
A-1
B-II
ITC
IDMA Invocation
The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the
intelligent DMA (IDMA).
IDMA request register
The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA
request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs.
When the IDMA request bit is set to "0", the corresponding interrupt factor does not invoke IDMA and a
normal interrupt processing will be performed. The IDMA request register is set to "0" by an initial reset.
The method by which this register is set can be selected from the software application using either of the two
methods described below. This selection is accomplished using IDMAONLY (D1) / Flag set/reset method
select register (0x4029F).
• Set-only method (default)
This method is selected (IDMAONLY = "1") when initially reset.
With this method, an IDMA request bit is set by writing "1". Although multiple IDMA request bits are
located in the IDMA request register, the IDMA request bits for which "0" has been written can be neither set
nor reset. Therefore, this method ensures that only a specific IDMA request bit is set.
However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit
that has been set to "1" is not reset by writing.
• Read/write method
This method is selected by writing "0" to IDMAONLY.
When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the
IDMA request bit is reset by writing "0" and set by writing "1". In this case, all IDMA request bits for which
"0" has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by
the hardware between the read and the write, so be careful when using this method.
IDMA enable register
To perform IDMA transfer using an interrupt factor, the corresponding bit of the IDMA enable register must
be set to "1". If this bit is set to "0", the interrupt factor cannot invoke the IDMA channel. The IDMA enable
register is set to "0" by an initial reset.
The IDMA enable register allows selection of a set method (set-only method or Read/write method) similar to
the IDMA request register. This selection is accomplished using DENONLY (D2) / Flag set/reset method
select register (0x4029F). See the above explanation for the set method.
Invoking IDMA
Before IDMA can be invoked by the occurrence of an interrupt factor, the corresponding bits of the IDMA
request and IDMA enable registers must be set to "1". Then when an interrupt factor occurs, the interrupt
request to the CPU is made pending and the corresponding IDMA channel is invoked. The DMA transfer is
performed according to the control information of that IDMA channel. The interrupt level set by the interrupt
priority register of the ITC does not affect the IDMA invocation. The IDMA request can be accepted even if
the interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when
generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled
using the interrupt level set by the interrupt priority register.
An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to
disable interrupts. It is also necessary that the control information for the IDMA channel has been set.