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II CORE BLOCK: BCU (Bus Control Unit)
B-II-4-42 EPSON S1C33L03 FUNCTION PART
RRA1–RRA0: Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E)
Select the RAS pulse width of a CAS-before-RAS refresh.
Table 4.27 Refresh RAS Pulse Width
RRA1 RRA0 Pulse width
11 5 cycles
10 4 cycles
01 3 cycles
00 2 cycles
The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
The RRA can be read to obtain their set value.
At cold start, RRA is set to "0" (2 cycles). At hot start, RRA retains its status before being initialized.
SBUSST: External interface method select register (D3) / Bus control register (0x4812E)
Select the interface method of an SRAM device.
Write "1": #BSL system
Write "0": A0 system
Read: Valid
When using the #BSL system, write "1" to SBUSST.
The contents set here are applied to all areas that are set for the SRAM type.
At cold start, SBUSST is set to "0" (A0 system). At hot start, SBUSST retains its status before being initialized.
SEMAS: External bus master setup (D2) / Bus control register (0x4812E)
Specify whether an external bus master exists.
Write "1": Existing
Write "0": Nonexistent
Read: Valid
A request for bus ownership control via the #BUSREQ pin is made acceptable by writing "1" to SEMAS. If the
system does not have any external bus master, fix this register at "0".
At cold start, SEMAS is set to "0" (nonexistent). At hot start, SEMAS retains its status before being initialized.
SEPD: External power-down control (D1) / Bus control register (0x4812E)
Enable or disable the CPU's power-down control by an external bus master.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Power-down control via an external pin (#BUSREQ) is enabled by writing "1" to SEPD. If the #BUSREQ pin is
lowered when external power-down control is thus enabled, the CPU is placed in a HALT state, allowing for
reduction in power consumption.
At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized.