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APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-23
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK
0 P12, etc.
P14, etc.
–
–
A18SZ
A18DF1
A18DF0
–
A18WT2
A18WT1
A18WT0
–
A16SZ
A16DF1
A16DF0
–
A16WT2
A16WT1
A16WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 18–17 device size selection
Areas 18–17
output disable delay time
reserved
Areas 18–17 wait control
reserved
Areas 16–15 device size selection
Areas 16–15
output disable delay time
reserved
Areas 16–15 wait control
–
–
–
1 8 bits 0 16 bits
1 8 bits 0 16 bits
–
0
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
0048120
(HW)
Areas 18–15
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A16DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A16WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A14DRA
A13DRA
A14SZ
A14DF1
A14DF0
–
A14WT2
A14WT1
A14WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 14 DRAM selection
Area 13 DRAM selection
Areas 14–13 device size selection
Areas 14–13
output disable delay time
reserved
Areas 14–13 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048122
(HW)
1
1
0
0
1
0
1
0
A14DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A14WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 14–13
set-up register