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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-13
A-1
B-VI
SDRAM
Power-up and Initialization
The following describes the processing sequence for powering up the SDRAM.
1. Setting the BCU and SDRAM access conditions
Set the BCU and the SDRAM controller as explained in "SDRAM Configuration".
2. SDRENA (D7)/SDRAM control register (0x39FFC1) = "1"
This causes the pins shown in Table 2.1 to be switched for SDRAM signal use. (The contents set in the port
function select and port function extension registers do not affect this switching.) Also, the BCLK pin starts
outputting the SDRAM clock.
Until this stage, the SDRAM pins shared with I/O ports are set for general-purpose input and placed in the high-
impedance state. If the power to the SDRAM is designed to be turned on simultaneously with the CPU, the
SDCKE (P20), HDQM (P32), and LDQM (P15) pins left floating may adversely affect the SDRAM, depending
on its specifications. (For example, unnecessary data may be output.) In such a case, these pins must be pulled
high, external to the chip. If the CPU and SDRAM are powered from separate power supplies and the power to
the SDRAM is turned on after writing "1" to SDRENA, the problem mentioned above does not occur, because
the signals for SDRAM use are being output.
3. Wait for 100 µs or more after turning on the power to the SDRAM
After the power to the SDRAM is turned on, the SDRAM must be held in an NOP state (#SDCEx = high) for at
least 100 µs. Because the duration of this period varies with each SDRAM, consult the specifications for your
SDRAM.
4. SDRINI (D6)/SDRAM control register (0x39FFC1) = "1"
This causes the SDRAM controller to output the commands in the order specified by the SDRIS (D4)/SDRAM
control register (0x39FFC1) in order to initialize the SDRAM. (Data are not initialized.)
SDRIS = "0": 1. Precharge → 2. Refresh → 3. Mode Register Set
SDRIS = "1": 1. Precharge → 2. Mode Register Set → 3. Refresh
Writing "1" to SDRINI has no effect when SDRENA = "0".
5. Checking SDRMRS (D7)/SDRAM status register (0x39FFCA)
SDRMRS is reset to "1" after power-on, and is set to "0" by executing the MRS (Mode Register Set) command.
Because the MRS command uses an external address bus, no other external devices can be accessed until its
output is finished. The SDRAM controller asserts the #WAIT signal provided for the user logic and keeps it
active until the MRS command output is finished after writing "1" to SDRINI, thus disabling external access
during that time. The CPU also ignores the no-wait access specified by SWAITE (D0/0x4812E) = "0". Before
initiating external access, however, be sure to check that SDRMRS is set to "0".
In addition to being reset at power-on, SDRMRS is reset to "1" by writing "0" to SDRENA or writing "1" to
SDRINI.
This completes the SDRAM initialization sequence, allowing access to the SDRAM.