Filter
Top Products
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-10 EPSON S1C33L03 FUNCTION PART
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in
advance. Transfer conditions, etc. must also be set on the IDMA side in advance.
Table 4.5 Control Bits for IDMA Transfer
Interrupt factor IDMA request bit IDMA enable bit
Timer 0 comparison A R16TC0(D7/0x40290) DE16TC0(D7/0x40294)
Timer 0 comparison B R16TU0(D6/0x40290) DE16TU0(D6/0x40294)
Timer 1 comparison A R16TC1(D1/0x40291) DE16TC1(D1/0x40295)
Timer 1 comparison B R16TU1(D0/0x40291) DE16TU1(D0/0x40295)
Timer 2 comparison A R16TC2(D3/0x40291) DE16TC2(D3/0x40295)
Timer 2 comparison B R16TU2(D2/0x40291) DE16TU2(D2/0x40295)
Timer 3 comparison A R16TC3(D5/0x40291) DE16TC3(D5/0x40295)
Timer 3 comparison B R16TU3(D4/0x40291)DE16TU3(D4/0x40295)
Timer 4 comparison A R16TC4(D7/0x40291) DE16TC4(D7/0x40295)
Timer 4 comparison B R16TU4(D6/0x40291) DE16TU4(D6/0x40295)
Timer 5 comparison A R16TC5(D1/0x40292) DE16TC5(D1/0x40296)
Timer 5 comparison B R16TU5(D0/0x40292) DE16TU5(D0/0x40296)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
High-speed DMA
The interrupt factor of each timer can also invoke high-speed DMA (HSDMA).
The following shows the HSDMA channel number and trigger set-up bit corresponding to each timer:
Table 4.6 HSDMA Trigger Set-up Bits
Interrupt factor HSDMA
Ch.
Trigger set-up bits
Timer 0 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"
Timer 0 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110"
Timer 1 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"
Timer 1 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110"
Timer 2 comparison A 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"
Timer 2 comparison B 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"
Timer 3 comparison A 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"
Timer 3 comparison B 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"
Timer 4 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"
2HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"
Timer 4 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"
2HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"
Timer 5 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"
3HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"
Timer 5 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"
3HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"
For HSDMA to be invoked, a 16-bit timer interrupt factor should be selected using the trigger set-up bits in
advance. Transfer conditions, etc. must also be set on the HSDMA side.
If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the
interrupt factor.
For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".