Filter
Top Products
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-9
A-1
B-III
16TM
16-Bit Programmable Timer Interrupts and DMA
The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B
states.
The timing at which an interrupt is generated is shown in Figure 4.2 in the preceding section.
Control registers of the interrupt controller
Table 4.4 shows the control registers of the interrupt controller provided for each timer.
Table 4.4 Control Registers of Interrupt Controller
Interrupt factor Interrupt factor flag Interrupt enable register Interrupt priority register
Timer 0 comparison A F16TC0 (D3/0x40282) E16TC0 (D3/0x40272) P16T0[2:0] (D[2:0]/0x40266)
Timer 0 comparison B F16TU0 (D2/0x40282) E16TU0 (D2/0x40272)
Timer 1 comparison A F16TC1 (D7/0x40282) E16TC1 (D7/0x40272) P16T1[2:0] (D[6:4]/0x40266)
Timer 1 comparison B F16TU1 (D6/0x40282) E16TU1 (D6/0x40272)
Timer 2 comparison A F16TC2 (D3/0x40283) E16TC2 (D3/0x40273) P16T2[2:0] (D[2:0]/0x40267)
Timer 2 comparison B F16TU2 (D2/0x40283) E16TU2 (D2/0x40273)
Timer 3 comparison A F16TC3 (D7/0x40283) E16TC3 (D7/0x40273) P16T3[2:0] (D[6:4]/0x40267)
Timer 3 comparison B F16TU3 (D6/0x40283) E16TU3 (D6/0x40273)
Timer 4 comparison A F16TC4 (D3/0x40284) E16TC4 (D3/0x40274) P16T4[2:0] (D[2:0]/0x40268)
Timer 4 comparison B F16TU4 (D2/0x40284) E16TU4 (D2/0x40274)
Timer 5 comparison A F16TC5 (D7/0x40284) E16TC5 (D7/0x40274) P16T5[2:0] (D[6:4]/0x40268)
Timer 5 comparison B F16TU5 (D6/0x40284) E16TU5 (D6/0x40274)
When a comparison match state occurs in the timer, the corresponding interrupt factor flag is set to "1".
If the interrupt enable register bit corresponding to that interrupt factor flag has been set to "1", an interrupt
request is generated.
An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to
"0". The interrupt factor flag is always set to "1" by the timer's comparison match state, regardless of how the
interrupt enable register is set (even when set to "0").
The interrupt priority register sets an interrupt priority level (0 to 7) for each timer. Priorities within a timer
block are such that timers of smaller numbers have a higher priority. Priorities between interrupt types are
such that the comparison B interrupt has priority over the comparison A interrupt. An interrupt request to the
CPU is accepted only when no other interrupt request of a higher priority has been generated.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer
interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the
CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Intelligent DMA
The interrupt factor of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory
DMA transfers to be performed cyclically.
The following shows the IDMA channel numbers set for each interrupt factor of timer:
IDMA Ch. IDMA Ch.
Timer 0 comparison B: 0x07 Timer 0 comparison A: 0x08
Timer 1 comparison B: 0x09 Timer 1 comparison A: 0x0A
Timer 2 comparison B: 0x0B Timer 2 comparison A: 0x0C
Timer 3 comparison B: 0x0D Timer 3 comparison A: 0x0E
Timer 4 comparison B: 0x0F Timer 4 comparison A: 0x10
Timer 5 comparison B: 0x11 Timer 5 comparison A: 0x12