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VII LCD CONTROLLER BLOCK: LCD CONTROLLER
B-VII-2-34 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VRAMAR
VRAMWT2
VRAMWT1
VRAMWT0
EDMAEN
BREQEN
LCDCST
LCDCEC
D7
D6
D5
D4
D3
D2
D1
D0
VRAM area select
VRAM wait control
(number of wait cycles for SRAM)
External DMA enable
External bus-request enable
A0/BSL select
Big/little endian select
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
039FFFD
(B)
1 Area 8 0 Area 7
1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 BSL 0 A0
1 Big endian 0
Little endian
LCDC
system control
register
0–7
Note:Addresses 0x39FFFE and 0x39FFFF are assigned for the purpose of inspecting the LCD
controller. Writing data to these addresses may damage the LCD controller and the LCD panel to
which the LCD controller is connected. Therefore, make sure data is never written to that location.
PCODE[5:0]: Product code (D[7:2]) / Revision code register (0x39FFE0)
The LCD controller’s product code (0b000010) is written here. These bits are read-only, and writing to them has
no effect.
RCODE[1:0]: Revision code (D[1:0]) / Revision code register (0x39FFE0)
The LCD controller’s revision code (0b00) is written here. These bits are read-only, and writing to them has no
effect.
LDCOLOR: Color/monochrome select (D5) / LCDC mode register 0 (0x39FFE1)
Selects the type of connected LCD panel (color or monochrome).
Write "1": Color panel
Write "0": Monochrome panel
Read: Valid
Setting LDCOLOR to "1" selects a color panel drive method, and setting it to "0" selects a monochrome panel
drive method.
At initial reset, LDCOLOR is set to "0" (monochrome panel).
FPSMASK: Mask FPSHIFT signal (D2) / LCDC mode register 0 (0x39FFE1)
Selects the FPSHIFT mask (effective only for color LCD panels).
Write "1": Masked
Write "0": Output
Read: Valid
When FPSMASK is set to "1", the FPSHIFT signal is masked and is not output during the non-display period.
When FPSMASK is set to "0", the FPSHIFT signal is output even during the non-display period. This setting is
effective only for color LCD panels (LDCOLOR = "1"). When a monochrome LCD panel is used, the FPSHIFT
signal is not masked regardless of the setting of this bit.
At initial reset, FPSMASK is set to "0" (output).
LDDW[1:0]: LCD data width/format (D[1:0]) / LCDC mode register 0 (0x39FFE1)
Selects the LCD panel’s data width and format. The contents of selection, including that of LDCOLOR, are listed
in Table 2.22.
Table 2.22 Selection of LCD Panels
LDCOLOR LDDW1 LDDW0 LCD panel
0Mono Single 4-bit passive LCD0
1Mono Single 8-bit passive LCD
0Reserved
0
1
1Reserved
0Color Single 4-bit passive LCD0
1Color Single 8-bit passive LCD format 1
0Reserved
1
1
1Color Single 8-bit passive LCD format 2
At initial reset, LDDW is set to "0b00" (4-bit panel).