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III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-3
A-1
B-III
I/O
I/O Memory of Input Ports
Table 9.2 shows the control bits of the input ports.
Table 9.2 Control Bits of Input Ports
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B)
1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
–
K54D
K53D
K52D
K51D
K50D
D7–5
D4
D3
D2
D1
D0
reserved
K54 input port data
K53 input port data
K52 input port data
K51 input port data
K50 input port data
– –
–
–
–
–
–
–
R
R
R
R
R
0 when being read.00402C1
(B)
1 High 0 Low
K5 input port
data register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C3
(B)
1 AD7 0 K67
1 AD6 0 K66
1 AD5 0 K65
1 AD4 0 K64
1 AD3 0 K63
1 AD2 0 K62
1 AD1 0 K61
1 AD0 0 K60
K6 function
select register
K67D
K66D
K65D
K64D
K63D
K62D
K61D
K60D
D7
D6
D5
D4
D3
D2
D1
D0
K67 input port data
K66 input port data
K65 input port data
K64 input port data
K63 input port data
K62 input port data
K61 input port data
K60 input port data
–
–
–
–
–
–
–
–
R
R
R
R
R
R
R
R
00402C4
(B)
1 High 0 LowK6 input port
data register
CFK54–CFK50: K5[4:0] function selection (D[4:0]) / K5 function select register (0x402C0)
CFK67–CFK60: K6[7:0] function selection (D[7:0]) / K6 function select register (0x402C3)
Selects the function of each input-port pin.
Write "1": Used for peripheral circuit
Write "0": Input port pin
Read: Invalid
When a bit of the CFK register is set to "1", the corresponding pin is set for use with the peripheral circuit (see
Table 9.1). The pins for which register bits are set to "0" can be used as general-purpose input ports.
At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset.
K54D–K50D: K5[4:0] input port data (D[4:0]) / K5 input port data register (0x402C1)
K67D–K60D: K6[7:0] input port data (D[7:0]) / K6 input port data register (0x402C4)
The input data on each input port pin can be read from this register.
Read "1": High level
Read "0": Low level
Write: Invalid
The pin voltage of each input port can be read out "1" directly when the voltage is high (V
DD) or "0" when the
voltage is low (V
SS) respectively.
Since this register is a read-only register, writing to the register is ignored.
When the ports set for A/D converter input are read, the value obtained is always "0".