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V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-26 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
S3ADRL15
S3ADRL14
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 source address[15:0]
S) Ch.3 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048254
(HW)
High-speed
DMA Ch.3
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE3
S3IN1
S3IN0
S3ADRH11
S3ADRH10
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transfer data size
D) Ch.3 source address control
S) Ch.3 memory address control
D) Ch.3 source address[27:16]
S) Ch.3 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048256
(HW)
1 Half word 0 Byte
High-speed
DMA Ch.3
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D3ADRL15
D3ADRL14
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048258
(HW)
High-speed
DMA Ch.3
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode