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CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE .................................... 83
4.1 Overview of Delayed Interrupt Generation Module ........................................................................... 84
4.2 Block Diagram of Delayed Interrupt Generation Module .................................................................. 85
4.3 Configuration of Delayed Interrupt Generation Module .................................................................... 86
4.3.1 Delayed interrupt request generate/cancel register (DIRR) ........................................................ 87
4.4 Explanation of Operation of Delayed Interrupt Generation Module .................................................. 88
4.5 Precautions when Using Delayed Interrupt Generation Module ....................................................... 89
4.6 Program Example of Delayed Interrupt Generation Module ............................................................. 90
CHAPTER 5 CLOCKS ..................................................................................................... 91
5.1 Clocks ............................................................................................................................................... 92
5.2 Block Diagram of the Clock Generation Block .................................................................................. 95
5.2.1 Register of Clock Generation Block ............................................................................................. 97
5.3 Clock Selection Register (CKSCR) ................................................................................................... 98
5.4 PLL/Subclock Control Register (PSCCR) ....................................................................................... 101
5.5 Clock Mode ..................................................................................................................................... 103
5.6 Oscillation Stabilization Wait Interval .............................................................................................. 107
5.7 Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 108
CHAPTER 6 CLOCK SUPERVISOR ............................................................................. 109
6.1 Overview of Clock Supervisor ......................................................................................................... 110
6.2 Block Diagram of Clock Supervisor ................................................................................................ 111
6.3 Clock Supervisor Control Register (CSVCR) .................................................................................. 113
6.4 Operating Mode of Clock Supervisor .............................................................................................. 115
CHAPTER 7 RESETS .................................................................................................... 119
7.1 Resets ............................................................................................................................................. 120
7.2 Reset Cause and Oscillation Stabilization Wait Times ................................................................... 123
7.3 External Reset Pin .......................................................................................................................... 125
7.4 Reset Operation .............................................................................................................................. 126
7.5 Reset Cause Bits ............................................................................................................................ 128
7.6 Status of Pins in a Reset ................................................................................................................ 132
CHAPTER 8 LOW-POWER CONSUMPTION MODE ................................................... 133
8.1 Overview of Low-Power Consumption Mode .................................................................................. 134
8.2 Block Diagram of the Low-Power Consumption Control Circuit ..................................................... 137
8.3 Low-Power Consumption Mode Control Register (LPMCR) ........................................................... 139
8.4 CPU Intermittent Operation Mode .................................................................................................. 142
8.5 Standby Mode ................................................................................................................................. 143
8.5.1 Sleep Mode ............................................................................................................................... 145
8.5.2 Watch Mode .............................................................................................................................. 148
8.5.3 Timebase Timer Mode ............................................................................................................... 150
8.5.4 Stop Mode ................................................................................................................................. 152
8.6 Status Change Diagram ................................................................................................................. 155
8.7 Status of Pins in Standby Mode and during Hold and Reset .......................................................... 156
8.8 Usage Notes on Low-Power Consumption Mode ........................................................................... 157