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CHAPTER 20 LIN-UART
■ Transmission interrupt request generation timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt
is generated.
Note:
A transmission interrupt is generated immediately after the transmission interrupt is enabled (SSR:
TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared
only by writing new data to the transmission data register (TDR). Carefully specify the transmission
interrupt enable timing.