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CHAPTER 20 LIN-UART
■ Transmission Data Register (TDR)
TDR is the data buffer register for serial data transmission. When data to be transmitted is written to the
transmission data register (TDR) in transmission enable state (SCR: TXE=1), it is transferred to the
transmission shift register, then converted to serial data, and transmitted from the serial data output pin
(SOTn pin). If the data length is 7 bits, the uppermost bit (TDR: D7) is invalid data.
When transmission data is written to this register, the transmission data empty flag bit (SSR: TDRE) is
cleared to 0. When transfer to the transmission shift register is completed and transmission starts, the bit is
set to 1. When the TDRE bit is 1, the next part of transmission data can be written. If transmission interrupt
requests have been enabled, a transmission interrupt is generated. Write the next part of transmission data
when a transmission interrupt is generated or the TDRE bit is 1.
Note:
TDR is a write-only register and RDR is a read-only register. These registers are located in the same
address, so the read value is different from the write value. Therefore, instructions that perform a read-
modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used.