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CHAPTER 5 CLOCKS
5.1 Clocks
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. The clock generated by the clock
generation block is called the machine clock. One cycle of machine clock is called one
machine cycle. The clock to be supplied from a high-speed oscillator is called an
oscillation clock, and the 2-frequency division of the oscillation clock is called a main
clock. The 4- or 2-frequency division of the clock supplied from a low-speed oscillator
or internal CR oscillation clock is called a sub-clock, and the clock by the PLL
oscillation is called PLL clock.
■ Clocks
The clock generation block contains the oscillation circuit that generates the oscillation clock by connecting
oscillator to oscillation pin. External clock inputted to the oscillation pins can be used as oscillation clock.
The clock generation block also contains the PLL clock multiplier circuit, which generates five clocks
whose frequencies are multiplication of the oscillation clock frequency. The clock generation block
controls the oscillation stabilization wait interval and PLL clock multiplication as well as internal clock
operation by changing the clock with a clock selector.
●
Oscillation clock (HCLK)
The oscillation clock is generated either by connecting the oscillator to high-speed oscillator pins (X0,X1)
or by the input of an external clock.
●
Main clock (MCLK)
The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input
to the timebase timer and the clock selector.
●
Sub-clock (SCLK)
The sub-clock is a clock by connecting the oscillator to the low-speed oscillation pins (X0A, X1A) or by
inputting the external clock or the internal CR oscillation clock divided by 4 or 2. The division ratio of sub-
clock is determined by SCDS bit of PLL/Subclock Control Register (PSCCR). The sub-clock can be used
as operation clock of the watch timer or the low-speed machine clock.
●
PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock frequency with the PLL clock multiplier
circuit (PLL oscillation circuit). One of five types of clocks can be selected by setting the multiplication
ratio selection bits (CKSCR: CS1, CS0, PSCCR: CS2)