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CHAPTER 6 CLOCK SUPERVISOR
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Main clock supervisor
The oscillation of the main oscillation clock (HCLK) is supervised by using the clock from the
CR oscillation circuit as a clock source.
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Sub clock supervisor
The oscillation of the sub oscillation clock (SCLK) is supervised by using the clock from the
CR oscillation circuit as a clock source.
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Control circuit
Disable or enable for main/sub clock supervisor, existence of internal reset generation when
clock halt condition is detected, and switching to CR oscillation clock of clock to be monitored
are controlled by setting of clock supervisor control register (CKSCR).
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Clock supervisor control register (CKSCR)
Disable or enable for main/sub clock supervisor, existence of internal reset generation when
clock halt condition is detected, or switching to CR oscillation clock of clock to be monitored
are selected.
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Main clock selector
CR oscillation clock is outputted as main clock when the main oscillation clock is missing.
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Sub clock selector
The divided clock of CR oscillation clock is outputted as sub clock when the sub oscillation
clock is missing.
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CR oscillation circuit
Internal CR oscillation clock circuit. Disable/enable the CR oscillation can be selected by the
control circuit.