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APPENDIX
■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control
registers of the MB90360 series.
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2)
Interrupt cause
EI
2
OS clear
DMA
channel
number
Interrupt vector Interrupt control register
Number ICR Address
Reset N #08
FFFFDC
H
--
INT9 instruction N #09
FFFFD8
H
--
Exception N #10
FFFFD4
H
--
Reserved N #11
FFFFD0
H
ICR00
0000B0
H
Reserved N #12
FFFFCC
H
CAN 1 RX N #13
FFFFC8
H
ICR01
0000B1
H
CAN 1 TX/NS N #14
FFFFC4
H
Reserved N #15
FFFFC0
H
ICR02
0000B2
H
Reserved N #16
FFFFBC
H
Reserved N #17
FFFFB8
H
ICR03
0000B3
H
Reserved N #18
FFFFB4
H
16-bit reload timer 2 Y1 #19
FFFFB0
H
ICR04
0000B4
H
16-bit reload timer 3 Y1 #20
FFFFAC
H
Reserved N #21
FFFFA8
H
ICR05
0000B5
H
Reserved N #22
FFFFA4
H
PPG C/D N #23
FFFFA0
H
ICR06
0000B6
H
PPG E/F N #24
FFFF9C
H
Time base timer N #25
FFFF98
H
ICR07
0000B7
H
External interrupt 8 to 11 Y1 #26
FFFF94
H
Watch timer N #27
FFFF90
H
ICR08
0000B8
H
External interrupt 12 to 15 Y1 #28
FFFF8C
H
A/D converter Y1 #29
FFFF88
H
ICR09
0000B9
H
I/O timer 0 N #30
FFFF84
H
Reserved N #31
FFFF80
H
ICR10
0000BA
H
Reserved N #32
FFFF7C
H
Input capture 0 to 3 Y1 #33
FFFF78
H
ICR11
0000BB
H
Reserved N #34
FFFF74
H
UART 0 RX Y2 #35
FFFF70
H
ICR12
0000BC
H
UART 0 TX Y1 #36
FFFF6C
H