Fujitsu F2MCTM-16LX Computer Hardware User Manual


 
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Last Event Indicator Register (LEIR)
Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (1 / 2)
Bit Name Function
bit7 NTE:
Node status transition
event bit
When this bit is 1, node status transition is the last event.
This bit is set to 1 after set either of bit of the control status register to "1"
(CSR:NTx=1).
This setting is not related to the setting of NIE bit of the control status register
(CSR).
At Write:
"0": Cleared
"1": No effect
At read by the instruction of the read-modify-write type:
Always read "1".
bit6 TCE:
Transmit completion
event bit
When this bit is 1, it indicates that transmit completion is the last event.
This bit is set to 1 after set either of bit of the transmit completion register to "1"
(TCR:TCx=1).
This setting is not related to the setting of the transmit interrupt enable register
(TIER).
When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to
complete the transmission of the message in the last event.
At Write:
"0": Cleared
"1": No effect
At read by the instruction of the read-modify-write type:
Always read "1".
bit5 RCE:
Receive completion
event bit
When this bit is 1, it indicates that receive completion is the last event.
This bit is set to 1 after set either of bit of the receive complete register to "1"
(RCR:RCx=1).
This setting is not related to the setting of the receive interrupt enable register
(RIER).
When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to
complete the transmission of the message in the last event.
At Write:
"0": Cleared
"1": No effect
At read by the instruction of the read-modify-write type:
Always read "1".
bit4 Undefined bit When reading: The value is undefined.
When writing: No effect