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CHAPTER 5 CLOCKS
5.5 Clock Mode
Three clock modes are provided: main clock mode, PLL clock mode and sub-clock
mode.
■ Clock Mode
●
Main clock mode
In main clock mode, a clock with 2-frequency division of the clock generated by connecting on oscillator
or by inputting from external to the high-speed oscillation pins (X0, X1) is used.
●
Sub-clock mode
In sub-clock mode, a clock with 4/2-frequency division of the clock generated by connecting an oscillator
or inputting from external, or the internal CR oscillation clock to the low-speed oscillation pins (X0A,
X1A) is used.
The subclock division ratio is determined by SCDS bit of PLL/subclock control register (PSCCR).
●
PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and PLL/
subclock control register (PSCCR: CS2).
■ Clock Mode Transition
Transition among main clock mode, PLL clock mode, and sub-clock mode is performed by writing to the
MCS and SCS bits of the clock selection register (CKSCR).
●
Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock
mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization
wait interval (2
14
/HCLK).
●
Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in PLL clock
mode, switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the
main clock coincide (after 1 to 12 PLL clocks).
●
Transition from main clock mode to sub-clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in main clock mode,
switching from the main clock to a sub-clock occurs by synchronizing with the subclock.