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CHAPTER 8 LOW-POWER CONSUMPTION MODE
❍
: operation,
✕
: stop,
◆
: held in the state before transiting, Hi-Z: High impedance
*1 : The timebase timer, watch timer, and low voltage detection function operate.
*2 : The watch timer operates.
*3 : The DTP/external interrupt input pin operates.
*4 : Watch timer, timebase timer, and external interrupts
*5 : Watch timer and external interrupts
*6 : External interrupt
MCS: PLL clock select bit in clock selection register (CKSCR)
SCS : Subclock select bit in the clock selection register (CKSCR)
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
SLP : Sleep mode bit of low-power consumption mode control register (LPMCR)
STP : Stop mode bit of low-power consumption mode control register (LPMCR)
TMD: Watch mode bit of low-power consumption mode control register (LPMCR)
Note:
For those external pins shared between port functions and peripheral functions in the stop mode, watch
mode, or timebase timer mode, disable output for the peripheral functions then set the STP bit to "1" or
reset the TMD bit to "0" to set these pins in high impedance state.