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CHAPTER 8 LOW-POWER CONSUMPTION MODE
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Return by interrupt
When an interrupt request higher than interrupt level (IL) of 7 is generated from the watch timer, timebase
timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled. After the
timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is
identified according to the settings of the I flag in the condition code register (CCR), the interrupt level
mask register (ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the next instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt
processing routine.
• The following two timebase timer modes are available:
- Main clock ←→ timebase timer mode
- PLL clock ←→ timebase timer mode
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the timebase timer mode has been specified. The CPU then proceeds
to interrupt processing.