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APPENDIX C Timing Diagrams in Flash Memory Mode
■ RY/BY Timing during Writing/erasing
Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/erasing
■ RST and RY/BY Timing
Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset
CE
WE
RY/
BY
t
BUSY
Rising edge of last write pulse
Writing or erasing
CE
RY/
BY
RST
t
RP
t
Ready