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CHAPTER 18 8-/10-BIT A/D CONVERTER
■ List of Registers and Reset Values of 8-/10-bit A/D Converter
Figure 18.3-1 List of Register and Reset Value of 8-/10-bit A/D Converter
■ Generation of Interrupt from 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register
(ADCR0, 1), the interrupt request flag bit in the A/D control status register (ADCS1:INT) is set to "1".
When an interrupt request is enabled (ADCS1:INTE = 1), an interrupt is generated.
A/D control status register (High)
15 14 13 12 11 10 9 8
Address
:000069
H
BUSY INT INTE PAUS STS1 STS0 STRT
−
ADCS1
R/W R/W R/W R/W R/W R/W W
7543210
MD1 MD0 S10
ADCS0
R/W R/W R/W R/W
ANS2 ANS1 ANS0 ANE2 ANE1ANE3 ANE0
R/W R/W R/W R/WR/W R/W R/W R/W
6
Address
:000068
H
−
A/D control status register (Low)
Data register (High)
15 14 13 12 11 10 9 8
Address
:00006B
H
− − − −−
D9
D8
ADCR1
76543210
Address
:00006A
H
D7
D6 D5 D4 D3 D2 D1 D0
ADCR0
RRRRRRRR
−−−−−−
−−−−
−−−−
RR
−
A/D setting register (High)
15 14 13 12 11 10 9 8
Address
:00006D
H
ST2 ST1 ST0 CT1CT2 CT0 ANS3
ADSR1
A/D setting register (Low)
76543210
Address
:00006C
H
ADSR0
00000000
B
00000000B
00000000B
XXXXXX00B
000XXXX0B
0000000XB
R/W R/W R/W R/W R/W R/W R/W R/W
X
W
R/W
R
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
: Read/Write
: Read only
: Write only
: Undefined bit
: Indeterminate
Reserved
Reserved
Data register (Low)
Reserved