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CHAPTER 20 LIN-UART
Figure 20.6-1 Baud Rate Selection Circuit of LIN-UART
EXT
REST
Txc = 0?
Txc = v/2?
OTO
1
0
1
0
FF
Rxc = 0?
Rxc = v/2?
FF
EXT
OTO
1
0
CLK
n=0,1
D14
D8
D13
D12
D11
D10
D9
D6
D7
D4
D5
D2
D3
D0
D1
Reload Value: v
Reception
15-bit Reload Counter
Transmission
15-bit Reload Counter
Reload Value: v
Count Value: T
XC
Reload
Reload
Reset
Start bit falling
edge detection
Reception
clock
Transmission
clock
SCKn
(external clock
input)
Reset
Reset
Set
Set
Internal data bus
SMRn
register
BGRn1
register
BGRn0
register