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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-6
Figure 6-1. Basic External Bus Cycles
State
A25:1, BHE#
BLE#, D/C#
M/IO#
W/R#
ADS#
NA#
D15:0
RD#
WR#
BS8#
READY#
LOCK#
T1 T2 T1 T2 Ti T1 T2 T1 T2
A2305-02
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
External
(Read)
Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
Cycle 4
Nonpipelined
External
(Read)
Idle
Cycle
REFRESH#
LBA#
CLK2
CLKOUT
Valid 1 Valid 2
Valid 3
Out 1 In 2
Out 3 In 4
Valid 1 Valid 2
Valid 3
Valid 4
Valid 4