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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-22
In cycle 3, NA# is sampled in the first T-state (T1P); the address and status have been valid for
one previous T-state and this is a new bus cycle. NA# is sampled active and — because a bus cy-
cle (cycle 4) is pending internally — the address, byte enables, and bus status signals for this
pending bus cycle (cycle 4) are driven during the next T2P state.
In cycle 4, NA# is sampled in the first T-state (T1P); the address and status have been valid for
one previous T-state, and this is a new bus cycle. NA# is sampled active and — because a bus
cycle is not internally pending — the address and byte enables go to an unknown state and the
bus status signals go inactive in the next T2i state. When this cycle is terminated by an active
READY# signal, there is no bus cycle pending internally and the bus enters the idle state (Ti).
From an idle bus, an additional overhead of one clock cycle is required to start a pipelined bus
cycle (this is true with all pipelined bus architectures). This additional clock is used to pipeline
the address and status signals for the first bus cycle in a train of pipelined bus cycles. As long as
back-to-back bus cycles are executed, the pipelined bus can maintain the same throughput as the
nonpipelined bus. Only when the bus pipeline gets broken (by entering an idle or hold state) is
the additional one-clock overhead required to start the pipe again for the next train of pipelined
bus cycles.
The first bus cycle after an idle bus state is always nonpipelined. Systems that use pipelining typ-
ically assert NA# during this cycle to enter pipelining. To initiate pipelining, this nonpipelined
cycle must be extended by at least one T-state so that the address and status can be pipelined be-
fore the end of the cycle. Subsequent cycles can be pipelined as long as no idle bus cycles occur.
Specifically, NA# is sampled at the start of phase 2 of any T-state in which the address and status
signals have been active for one T-state and a new cycle has begun:
• The first T2 state of a nonpipelined cycle (the second T-state)
• The T1P state of a pipelined cycle (the first T-state)
• Any wait state of a nonpipelined or pipelined cycle unless NA# has already been sampled
active
Once NA# is sampled active, it remains active internally throughout the current bus cycle. When
NA# and READY# are active in the same T2 state, the state of NA# is irrelevant because
READY# causes the start of a new bus cycle. Therefore, the new address and status signals are
always driven, regardless of the state of NA#. NA# has no effect on a refresh cycle because the
refresh cycle is entered from an idle bus state and exits to an idle bus state.
With this processor, address pipelining is optional so that bus cycle timing can be closely tailored
to the access time of the memory device.
• Pipelining can be activated once the address is latched externally.
• Pipelining can be not activated if the address is not latched.
For systems that use address pipelining, the great majority of accesses are pipelined. Very few
idle states occur in an Intel386 EX processor system. This means that once the processor has en-
tered pipelining, another bus cycle request is almost always internally pending, resulting in a con-
tinuous train of pipelined cycles. In measured systems, about 85% of bus cycles are pipelined.