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CONTENTS
FIGURES
Figure Page
17-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL)....................................17-10
17-5 Power Control Register (PWRCON).........................................................................17-11
18-1 Test Logic Unit Connections ......................................................................................18-2
18-2 TAP Controller (Finite-State Machine)........................................................................18-6
18-3 Instruction Register (IR)..............................................................................................18-7
18-4 Identification Code Register (IDCODE)......................................................................18-8
18-5 Internal and External Timing for Loading the Instruction Register............................18-12
18-6 Internal and External Timing for Loading a Data Register........................................18-13
B-1 Derivation of AEN Signal in a Typical PC/AT System................................................. B-3
B-2 Derivation of AEN Signal for Intel386™ EX processor-based Systems...................... B-3
E-1 General Instruction Format........................................................................................ E-22