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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
8-4
vice enters the programmed mode when the HALT cycle is terminated by a valid READY#. This
READY# may be generated either internally or externally.
A device reset, an NMI or SMI#, or any unmasked interrupt request from the interrupt control
unit causes the device to exit the power management mode. After a reset, the CPU starts execut-
ing instructions at 3FFFFF0H and the device remains in normal operation. After an interrupt, the
CPU executes the interrupt service routine, then returns to the instruction following the HALT
that prompted the power management mode. Unless software modifies the power control register,
the next HALT instruction returns the device to the programmed power management mode.
8.1.2.1 SMM Interaction with Power Management Modes
When the processor receives an SMI# interrupt while it is in idle or powerdown mode, it exits the
power management mode and enters System Management Mode (SMM). Upon exiting SMM,
software can check whether the processor was in a halt state before entering SMM. If it was, soft-
ware can set a flag that returns the processor to the halt state when it exits SMM. Assuming the
power control register bits were not altered in SMM, the processor re-enters idle or powerdown
when it exits SMM. Figure 8-3 illustrates the relationships among these modes.