Filter
Top Products
3-1
CHAPTER 3
CORE OVERVIEW
The Intel386™ EX processor core is based upon the Intel386 CX processor, which is an enhanced
version of the Intel386 SX processor. This chapter describes the Intel386 CX processor enhance-
ments over the Intel386 SX processor, internal architecture of the Intel386 CX processor, and the
core interface on the Intel386 EX processor.
This chapter is organized as follows:
• Intel386 CX Processor Enhancements (see below)
• Intel386 CX Processor Internal Architecture (page 3-2)
• Core Intel386 EX Processor Interface (page 3-6)
3.1 Intel386 CX PROCESSOR ENHANCEMENTS
The Intel386 CX processor, based on the Intel386 SX processor, adds system management mode
and two additional address lines for a total of 26 address lines.
3.1.1 System Management Mode
The Intel386 CX processor core provides a mechanism for system management with a combina-
tion of hardware and CPU microcode enhancements. An externally generated System Manage-
ment Interrupt (SMI#) allows the execution of system wide routines which are independent and
transparent to the operating system. The System Management Mode (SMM) architecture exten-
sions to the Intel386 SX processor consist of the following elements:
• Interrupt input pin (SMI#) to invoke SMM
• One output pin to identify execution state (SMIACT#)
• One new instruction (RSM, executable only from SMM) to exit SMM
• SMM also added one to four execution clocks to the following instructions: IN, INS, REP
INS, OUT, REP OUT, POPA, HALT, MOV CR0, and SRC. INTR and NMI also need an
additional two clocks for interrupt latency. These cycles were added due to the microcode
modification for the SMM implementation. Refer to Appendix E for the exact execution
times. Otherwise, 100% of the Intel386 SX processor instructions execute on the Intel386
CX processor core.
Please refer to Chapter 7 for more details on System Management Mode.
3.1.2 Additional Address Lines
Two additional address lines were added to the Intel386 CX processor core for a total of 26. This
expands the physical address space from 16 Mbytes to 64 Mbytes.