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Index-3
INDEX
D
Deassert, defined, 1-4
Decoding techniques, I/O address, 4-6
Design considerations
clock and power management unit,
8-11
input/output ports, 16-10
interrupt control unit, 9-29–9-30
JTAG test-logic unit, 18-14
refresh control unit, 15-11
synchronous serial I/O unit, 13-25
Device configuration, 5-1–5-37
procedure, 5-28
register addresses, 4-19, D-5
worksheets, 5-34–5-37
DMA controller, 12-1–12-61
block diagram, 12-2
configuring, 5-3
departures from PC/AT architecture, B-1–B-3
DMACLR command, 12-50
DMACLRBP command, 12-50
DMACLRMSK command, 12-50
DMACLRTC command, 12-50
interrupts, 12-26–12-27
operation, 12-5–12-27
8237A compatibility, 12-27
basic refresh cycle, 15-5
buffer-transfer modes, 12-12
bus control arbitration, 12-9
bus cycle options for data transfers, 12-5–
12-8
cascade mode, 12-25–12-26
changing priority of DMA channel and
external bus requests,
12-10
data-transfer modes
block,
12-18–12-20
demand, 12-21–12-24
single, 12-14–12-17
DMA transfers, 12-5
ending DMA transfers, 12-10
starting DMA transfers, 12-9
overview, 12-1–12-4
programming, 12-28–12-51
address and byte count registers, 12-33
channel registers, 12-33
considerations, 12-50
DMA0BYCn, 12-33, D-24
DMA0REQn, 12-33, D-24
DMA0TARn, 12-33, D-24
DMA1BYCn, 12-33, D-24
DMA1REQn, 12-33, D-24
DMA1TARn, 12-33, D-24
DMABSR register,
12-46
DMACFG, 5-6, 12-32, D-14
DMACFG register, 12-32
DMACHR, 12-47, D-15
DMACHR register, 12-47
DMACMD1, 12-35, D-16
DMACMD1 register, 12-35
DMACMD2, 12-37, D-17
DMACMD2 register, 12-37
DMAGRPMSK, 12-45, D-18
DMAIEN, 12-48, D-19
DMAIEN register, 12-48
DMAIS, 12-49, D-20
DMAIS register, 12-49
DMAMOD1, 12-39, D-21
DMAMOD1 register, 12-38
DMAMOD2, 12-41, D-22
DMAMOD2 register, 12-40–12-41
DMAMSK, 12-44, D-23
DMAOVFE register, 12-34
DMASRR, 12-43, D-26
DMASRR register, 12-42, 12-43
DMASTS, 12-36, D-27
DMASTS register, 12-36
PINCFG register, 12-28, 12-31
register addresses, 4-15, D-1
registers, 12-28
signals, 12-4
using with external devices, 5-3
Documents, related, 1-5
DOS Address, defined, 1-4