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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
11-6
11.2.2 SIO
n
Transmitter
The data frame for transmissions is programmable. It consists of a start bit, 5 to 8 data characters,
an optional parity bit, and 1 to 2 stop bits. The transmitter can produce even, odd, forced, or no
parity. The transmitter can also produce break conditions. A break condition forces the serial out-
put (TXDn) to the spacing (logic 0) state for longer than a transmission time (the time of the start
bit + data bits + parity bit + stop bits). On the receiving end, a break condition sets an error flag.
Forced parity (“sticky bit”) allows the SIO to be used in multiprocessor communications. When
using forced parity the serial port uses the parity bit to distinguish between address and data bytes.
Forced parity is enabled in the SIO by setting the PEN and SP bits in the serial line control register
(Figure 11-15). When enabled for forced parity, the bit that is transmitted in the parity bit location
is the complement of the EPS bit (also in the serial line control register). In the receiver, if PEN
and SP are 1, the receiver compares the bit that is received in the parity bit location with the com-
plement of the EPS bit. If the values being compared are not equal, the receiver sets the Parity
Error bit in LSR and causes an error interrupt if line status interrupts are enabled.
For example, if forced parity is enabled and EPS is 0, the receiver expects the bit received at the
parity bit location to be 1. If it is not, the parity error bit is set. By forcing the bit value at the parity
bit location, rather than calculating a parity value, a system with a master transmitter and multiple
receivers can identify some transmitted characters as receiver addresses and the rest of the char-
acters as data. If PEN = 0, the SP bit is ignored.
Each SIO channel transmitter contains a transmit shift register, a transmit buffer, and a transmit
data pin (TXDn). Data to be transmitted is written to the transmit buffer. The transmitter then
transfers the data to the transmit shift register. The transmitter shifts the data along with asynchro-
nous communication bits (start, stop, and parity) out via the TXDn pin. The TXD0 and TXD1
pins are multiplexed with other functions. The pin configuration registers (PINCFG and P2CFG)
determine whether a TXDn signal or an alternate function is connected to the package pin.