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E-7
INSTRUCTION SET SUMMARY
IDIV = Integer divide (signed)
Accumulator by
register/memory
1 1 1 1 0 1 1 w mod 111 r/m
divisor
— byte
— word
— doubleword
19/22
27/30
43/48
19/22
27/30
43/48
b, e
b, e
b, e
e, h
e, h
e, h
AAD = ASCII adjust for
divide
1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
19 19
AAM = ASCII adjust for
multiply
1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0
17 17
CBW = Convert byte to
word
1 0 0 1 1 0 0 0
33
CWD = Convert word to
double-word
1 0 0 1 1 0 0 1
22
LOGIC
shift rotate instructions
not through carry (ROL, ROR, SAL, SAR, SHL, and SHR)
register/memory by 1 1 1 0 1 0 0 0 w mod TTT r/m 3/7** 3/7** b h
register/memory by CL 1 1 0 1 0 0 1 w mod TTT r/m 3/7* 3/7* b h
register/memory by
immediate count
1 1 0 0 0 0 0 w mod TTT r/m immed 8-bit data
3/7* 3/7* b h
through carry (RCL and RCR)
register/memory by 1 1 1 0 1 0 0 0 w mod TTT r/m 9/10* 9/10* b h
register/memory by CL 1 1 0 1 0 0 1 w mod TTT r/m 9/10* 9/10* b h
register/memory by
immediate count
1 1 0 0 0 0 0 w mod TTT r/m immed 8-bit data
9/10* 9/10* b h
T T T
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
Instruction
ROL
ROR
RCL
RCR
SHL/SAL
SHR
SAR
SHLD = Shift left double
register/memory by
immediate
0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 mod reg r/m
immed
8-bit data
3/7** 3/7**
register/memory by CL 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 mod reg r/m 3/7** 3/7**
Table E-1. Instruction Set Summary (Sheet 6 of 19)
Instruction Format
Clock Count Notes
Real
Ad-
dress
Mode
or
Virtual
8086
Mode
Pro-
tected
Virtual
Ad-
dress
Mode
Real
Ad-
dress
Mode
or
Virtual
8086
Mode
Pro-
tected
Virtual
Ad-
dress
Mode