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17-1
CHAPTER 17
WATCHDOG TIMER UNIT
The watchdog timer (WDT) unit can function as a general-purpose timer, a software watchdog
timer, or a bus monitor, or it can be disabled.
This chapter is organized as follows:
• Overview (see below)
• Watchdog Timer Unit Operation (page 17-3)
• Disabling the WDT (page 17-6)
• Register Definitions (page 17-7)
• Design Considerations (page 17-12)
• Programming Considerations (page 17-12)
17.1 OVERVIEW
The watchdog timer unit (Figure 17-1) includes a 32-bit reload register, a 32-bit down-counter,
an 8-state binary counter, a readable counter value register, and a status register.
The watchdog timer can operate in three modes:
• General-purpose 32-bit timer/counter mode (default mode)
• Watchdog mode
• Bus-monitor mode
Only a single mode can be active at one time. If you have no need for any of its functions, you
can disable the unit entirely.
Watchdog mode protects systems from software upsets. In watchdog mode, system software must
reload the down-counter at regular intervals. If it fails to do so, the timer expires and asserts
WDTOUT. For example, the watchdog times out if the software goes into an endless loop.
Some possible uses of this feature include:
• Connecting WDTOUT to the NMI pin to generate a non-maskable interrupt
• Connecting the WDTOUT signal to the RESET pin to reset the processor (and possibly the
entire system)
In watchdog mode only, idle mode stops the down-counter. Since no software can execute while
the CPU is idle, a software watchdog is unnecessary. (Chapter 8, “CLOCK AND POWER MAN-
AGEMENT UNIT,” discusses idle mode.)
Bus monitor mode protects normally not-ready systems from ready-hang conditions. (A normally
not-ready system is one in which a bus cycle continues until the accessed device asserts