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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
3-4
The six functional units of the Intel386 CX processor are:
• Core Bus Unit
• Instruction Prefetch Unit
• Instruction Decode Unit
• Execution Unit
• Segmentation Unit
• Paging Unit
3.2.1 Core Bus Unit
The Core Bus Unit provides the interface between the processor and its environment. It accepts
internal requests for instruction fetches (from the Instruction Prefetch Unit) and data transfers
(from the Execution Unit), and prioritizes the requests. At the same time, it generates or processes
the signals to perform the current bus cycle. These signals include the address, data, and control
outputs for accessing external memory and I/O. The Core Bus Unit also controls the interface to
external bus masters and coprocessors.
3.2.2 Instruction Prefetch Unit
The Instruction Prefetch Unit performs the program look ahead function of the CPU. When the
Core Bus Unit is not performing bus cycles to execute an instruction, the Instruction Prefetch Unit
uses the Core Bus Unit to fetch sequentially along the instruction byte stream. These prefetched
instructions are stored in the Instruction Queue to await processing by the Instruction Decode
Unit.
Instruction prefetches are given a lower priority than data transfers; assuming zero wait state
memory access, prefetch activity never delays execution. On the other hand, when there is no data
transfer requested, prefetching uses bus cycles that would otherwise be idle.
3.2.3 Instruction Decode Unit
The Instruction Decode Unit takes instruction stream bytes from the Prefetch Queue and trans-
lates them into microcode. The decoded instructions are then stored in a three-deep Instruction
Queue (FIFO) to await processing by the Execution Unit. Immediate data and opcode offsets are
also taken from the Prefetch Queue. The decode unit works in parallel with the other units and
begins decoding when there is a free slot in the FIFO and there are bytes in the prefetch queue.
Opcodes can be decoded at a rate of one byte per clock. Immediate data and offsets can be decod-
ed in one clock regardless of their length.