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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-12
Figure 6-4 shows internal and external bus cycles.
Figure 6-4. Basic Internal and External Bus Cycles
State
A25:1, BHE#
BLE#, D/C#
M/IO#
W/R#
ADS#
NA#
D15:0
RD#
WR#
BS8#
LOCK#
T1 T2 T1 T2 T1 T2 Ti T1 T2
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
Internal
(Read)
Cycle 3
Nonpipelined
Internal
(Write)
[Early Ready]
Cycle 4
Nonpipelined
External
(Read)
REFRESH#
LBA#
CLK2
CLKOUT
Valid 1 Valid 2
Valid 3
Out 1
Valid 1 Valid 2
Valid 3
In
2
Out 3
In
4
Idle
Cycle
Idle
Cycle
Idle
Cycle
Ti Ti
End Cycle 1
End Cycle 2
End Cycle 3
READY#
End Cycle 4
Valid 4
Valid 4
A2486-03