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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
3-2
3.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE
The internal architecture of the Intel386 CX processor consists of functional units that operate in
parallel. Fetching, decoding, execution, memory management and bus accesses for several in-
structions are performed simultaneously. This parallel operation is called pipelined instruction
processing. With pipelining, each instruction is performed in stages, and the processing of several
instructions at different stages may overlap, as shown in Figure 3-1. The pipelined processing of
the Intel386 CX processor results in higher performance and enhanced throughput rate over non-
pipelined processors.
Figure 3-1. Instruction Pipelining
Elapsed Time
Typical
Processor
386™ SX CPU/376™ CPU
Fetch 1 Decode 1 Execute 1 Fetch 2 Decode 2 Execute 2
Bus Unit
Fetch 1
Fetch 4
Fetch 2 Fetch 3
Store
Result 1
Fetch 5 Fetch 6
Decode 1 Decode 2 Decode 3 Decode 4 Decode 5
Decode
Unit
Execute 2 Execute 3 Execute 4
Execution
Unit
Execute 1
Addr &
MMU
Addr &
MMU
A2850-01
MMU
Intel386™ SX CPU/Intel376™ CPU