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6-9
BUS INTERFACE UNIT
NOTE
Pipelining is also supported during memory cycles initiated by the two
integrated DMA units.
Refer to “Pipelined Cycle” on page 6-19 for a description of pipelined cycles.
6.2.3 Data Bus Transfers and Operand Alignment
The processor can address up to 64 Mbytes (2
26
bytes, addresses 0000000H–3FFFFFFH) of
physical memory and up to 64 Kbytes (2
16
bytes, addresses 0000H–FFFFH) of I/O. The device
maintains separate physical memory and I/O spaces.
A programmer views the address space (memory or I/O) as a sequence of bytes:
• Words consist of 2 consecutive bytes
• Doublewords consist of 4 consecutive bytes
However, in the system hardware, address space is implemented in 2-byte portions. When the
processor reads a word, it accesses a byte from each portion of the 16-bit data bus. The processor
automatically translates the programmer’s view of consecutive bytes into this hardware imple-
mentation.
Memory and I/O spaces are organized physically as sequences of 16-bit words (2
25
16-bit mem-
ory locations and 2
15
16-bit I/O ports maximum). Each word starts at a physical address that is a
multiple of 2 and has 2 individually addressable bytes at consecutive addresses.
Pins A25:1 correspond to the most-significant bits of the physical address; these pins address
words of memory. The least-significant bit of the physical address is used internally to activate
the appropriate byte enable outputs (BHE# or BLE# or both).
Data can be transferred in quantities of either 8 or 16 bits for each bus cycle of a data transfer.
When a data transfer can be completed in a single cycle, the transfer is said to be aligned. For
example, a word transfer involving D15:0 and activating BHE# and BLE# is aligned.
Word transfers that cross a word boundary or doubleword transfers that cross two word bound-
aries are called nonaligned transfers. Nonaligned word transfers require two bus cycles, while
nonaligned doubleword transfers require three. The processor automatically generates these cy-
cles. For example:
• A word (16-bit) transfer at (byte) address 03H requires two byte transfers:
— The first activates word address 04H and uses D7:0 (to write or read the upper byte of
the 16-bit word)
— The second activates word address 02H and uses D15:8 (to write or read the lower byte
of the 16-bit word)