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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
9-34
Real/Protected Mode
No changes required.
*****************************************************************************/
int InitICU(BYTE MstrMode, BYTE MstrBase, BYTE MstrCascade, BYTE SlaveMode,
BYTE SlaveBase, BYTE MstrPins, BYTE SlavePins)
{
BYTE icw, cfg_pins;
/* Program Slave ICU */
_IRQ_SlaveBase_ = SlaveBase & 0xf8;
_SetEXRegByte(ICW1S, 0x11 | SlaveMode);// Set slave triggering
_SetEXRegByte(ICW2S, _IRQ_SlaveBase_); // Set slave base interrupt type,
// least 3-bit must be 0
_SetEXRegByte(ICW3S, 0x2); // Set slave ID
_SetEXRegByte(ICW4S, 0x1); // Set bit 0 to guarantee operation
/* Program Master ICU */
_IRQ_MstrBase_ = MstrBase & 0xf8;
_CascadeBits_ = MstrCascade | 0x4;
icw = (MstrMode & ICU_TRIGGER_LEVEL) ? 0x19 : 0x11;
_SetEXRegByte(ICW1M, icw); // Set master triggering
_SetEXRegByte(ICW2M, _IRQ_MstrBase_); // Set master base interrupt
// type, least 3-bit must be 0
_SetEXRegByte(ICW3M, _CascadeBits_); // Set master cascade pins,
// Make sure IR2 set for Cascade
icw = (MstrMode & ~ICU_TRIGGER_LEVEL) | 1;// Set bit 0 and remove
// Trigger_level bit (in ICW1)
_SetEXRegByte(ICW4M, icw); // Set slave IDs in master
/* Program chip configuration registers */
cfg_pins = _GetEXRegByte(INTCFG);
if( (MstrCascade & 0xfb) != 0 ) // bit 2 (IR2) is internal,
// external signals not required
// for just IR2
cfg_pins |= 0x80; // Using external slaves,
// therefore enable Cascade signals
cfg_pins |= SlavePins;
_SetEXRegByte(INTCFG, SlavePins); // Set Slave external interrupt pins
cfg_pins = _GetEXRegByte(P3CFG); // Preserve other set bits
_SetEXRegByte(P3CFG, cfg_pins | MstrPins);// Set Master external
// interrupt pins
return E_OK;
}/* InitICU */