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INTERRUPT CONTROL UNIT
Figure 9-3. Interrupt Process – Master Request from Non-slave Source
A2427-01
Master receives an interrupt request. (From a non-slave source.)
Master sets the request's pending bit.
Is
request
enabled?
Is
special
mask mode
enabled?
Is master
operating in
special-fully
nested
mode?
(operating in
fully nested
mode)
Is
the
in-service
bit for this
request
set?
Is
request
higher level
than any set
in-service
bits?
Is
request
equal or higher
than any set
in-service
bits?
Master sends request to CPU. CPU initiates interrupt acknowledge cycle.
Master clears request's pending bit, sets its in-service bit, and puts its
interrupt vector number on the bus.
An interrupt return instruction is issued, ending the interrupt process.
Is
master in
AEOI
mode?
Master clears its in-service bit. The
CPU uses its operating mode and the
interrupt vector number to find the
interrupt service routine's address.
CPU begins processing interrupt.
The interrupt service routine sends an EOI command, causing the master
to clear its in-service bit.
End
Yes No No
YesYesNo
Yes No No
YesYesNo
Yes
No
The CPU uses its operating mode and the interrupt vector number to find
the interrupt service routine's address. CPU begins processing interrupt.