Filter
Top Products
13-19
SYNCHRONOUS SERIAL I/O UNIT
13.3.3 Prescale Clock Register (CLKPRS)
Use CLKPRS to program the PSCLK frequency.
Figure 13-17. Clock Prescale Register (CLKPRS)
Clock Prescale Register
CLKPRS
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F804H
—
0000H
15 8
———— ———PS8
7 0
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
Bit
Number
Bit
Mnemonic
Function
15–9 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
8–0 PS8:0 Prescale Value:
These bits determine the divisor that is used to generate PSCLK. Legal
values are from 0000H (divide by 2) to 01FFH (divide by 513).
divisor = PS8:0 + 2