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xix
CONTENTS
FIGURES
Figure Page
11-21 Modem Control Register (MCR
n
).............................................................................11-30
11-22 Modem Status Register (MSR
n
)...............................................................................11-31
11-23 Scratch Pad Register (SCR
n
)...................................................................................11-32
12-1 DMA Unit Block Diagram............................................................................................12-2
12-2 DMA Temporary Buffer Operation for a Read Transfer..............................................12-8
12-3 DMA Temporary Buffer Operation for A Write Transfer .............................................12-8
12-4 Start of a Two-cycle DMA Transfer Initiated by DRQ
n
...............................................12-9
12-5 Changing the Priority of the DMA Channel and External Bus Requests..................12-10
12-6 Buffer Transfer Ended by an Expired Byte Count ....................................................12-11
12-7 Buffer Transfer Ended by the EOP# Input................................................................12-11
12-8 Single Data-transfer Mode with Single Buffer-transfer Mode ...................................12-15
12-9 Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode.........................12-16
12-10 Single Data-transfer Mode with Chaining Buffer-transfer Mode...............................12-17
12-11 Block Data-transfer Mode with Single Buffer-transfer Mode ....................................12-19
12-12 Block Data-transfer Mode with Autoinitialize Buffer-transfer Mode..........................12-20
12-13 Buffer Transfer Suspended by the Deactivation of DRQ
n
........................................12-21
12-14 Demand Data-transfer Mode with Single Buffer-transfer Mode................................12-22
12-15 Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode .....................12-23
12-16 Demand Data-transfer Mode with Chaining Buffer-transfer Mode ...........................12-24
12-17 Cascade Mode .........................................................................................................12-26
12-18 Pin Configuration Register (PINCFG).......................................................................12-31
12-19 DMA Configuration Register (DMACFG)..................................................................12-32
12-20 DMA Channel Address and Byte Count Registers
(DMA
n
REQ
n
, DMA
n
TAR
n
, DMA
n
BYC
n
).................................................................12-33
12-21 DMA Overflow Enable Register (DMAOVFE)...........................................................12-34
12-22 DMA Command 1 Register (DMACMD1).................................................................12-35
12-23 DMA Status Register (DMASTS)..............................................................................12-36
12-24 DMA Command 2 Register (DMACMD2).................................................................12-37
12-25 DMA Mode 1 Register (DMAMOD1) ........................................................................12-39
12-26 DMA Mode 2 Register (DMAMOD2) ........................................................................12-41
12-27 DMA Software Request Register (DMASRR – write format)....................................12-42
12-28 DMA Software Request Register (DMASRR – read format) ....................................12-43
12-29 DMA Channel Mask Register (DMAMSK)................................................................12-44
12-30 DMA Group Channel Mask Register (DMAGRPMSK).............................................12-45
12-31 DMA Bus Size Register (DMABSR) .........................................................................12-46
12-32 DMA Chaining Register (DMACHR).........................................................................12-47
12-33 DMA Interrupt Enable Register (DMAIEN) ...............................................................12-48
12-34 DMA Interrupt Status Register (DMAIS)...................................................................12-49
13-1 Transmitter and Receiver in Master Mode .................................................................13-2
13-2 Transmitter in Master Mode, Receiver in Slave Mode................................................13-2
13-3 Transmitter in Slave Mode, Receiver in Master Mode................................................13-3
13-4 Transmitter and Receiver in Slave Mode ...................................................................13-3
13-5 Clock Sources for the Baud-rate Generator...............................................................13-5
13-6 SSIO Transmitter with Autotransmit Mode Enabled...................................................13-7