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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-40
The interface has these characteristics:
• The Intel387 SX Math Coprocessor shares the local bus of the Intel386 EX processor.
• The Intel386 EX processor and Intel387 SX Math Coprocessor share the same reset signals.
They also share the same clock input.
• The corresponding BUSY#, ERROR#, and PEREQ pins are connected together.
• The Status Enable (STEN) selects the math coprocessor. It causes the chip to recognize
other chip select inputs. STEN is tied high.
• CKM is tied high to select the synchronous mode of operation for the coprocessor.
• The math coprocessor NPS1# and NPS2 inputs are connected to the Intel386 EX processor
M/IO# and A23 inputs respectively. For math coprocessor cycles, M/IO# is always LOW
and A23 always HIGH.
• The math coprocessor input CMD0 is connected to the A2 output. The Intel386 EX
embedded processor generates address 8000F8H when writing a command and address
8000FCH or 8000FEH (treated as 8000FCH by the Intel387 SX Math Coprocessor) when
writing or reading data. It does not generate any other addresses during Intel387 SX Math
Coprocessor bus cycles.
CAUTION
A chip-select signal could go active during coprocessor cycles if a match for
the lower 16 bits of address is found in one of the chip-select regions of the
Chip-select Unit. This can happen because only the lower 16 bits are decoded
by the Chip-select Unit during I/O cycles.
• The READYO# pin of the coprocessor must be sent through a buffer to prevent the Intel386
EX processor and coprocessor from simultaneously driving the READY# pin. The buffer is
enabled using the LBA# pin. During internal bus cycles, the LBA# pin is asserted and the
Intel386 EX processor provides the READY# signal. In a coprocessor access, the LBA# is
deasserted, the external buffer is enabled, and the coprocessor provides the READY# signal
to the Intel386 EX processor.
6.6.1.2 Software Considerations
To enable math-coprocessor support in the Intel386 EX processor, you must set the MP (Math
Present) bit and clear the EM (Coprocessor Emulation) bit in the Machine Status Word (lower
half of the CR0 register in the core). This can be done using the following code:
smsw ax ;; Store Machine Status Word into AX
or ax, 2 ;; Set MP bit
and ax, 0fffbh ;; Clear EM bit
lmsw ax ;; Load AX into Machine Status Word