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9-1
CHAPTER 9
INTERRUPT CONTROL UNIT
The Interrupt Control Unit (ICU) consists of two cascaded interrupt controllers, a master and a
slave, that allow internal peripherals and external devices (through interrupt pins) to interrupt the
core through its interrupt input.
The interrupt control unit is functionally identical to two industry-standard 82C59As connected
in cascade. The system supports a maximum of 15 simultaneous interrupt sources, which can be
individually or globally disabled. The ICU passes the interrupts on to the core based on a pro-
grammable priority structure.
Though the ICU can only handle a maximum of 15 simultaneous sources, a total of 18 interrupt
sources can be connected to the ICU. Eight of these interrupt sources come from internal periph-
erals and the other ten come from external pins. To increase the number of possible interrupts,
you can cascade additional 82C59As to six of the external interrupt pins (the pins that connect to
the master 82C59A only).
This chapter describes the interrupt control unit and is organized as follows:
• Overview (see below)
• ICU operation (page 9-4)
• Register Definitions (page 9-15)
• Design Considerations (page 9-29)
• Programming Considerations (page 9-32)
9.1 OVERVIEW
The ICU consists of two 82C59As configured as master and slave. Each 82C59A has eight inter-
rupt request (IR) signals. The master has seven interrupt sources and a slave 82C59A connected
to its IR signals. The slave has nine interrupt sources connected to its IR signals (two sources are
multiplexed into IR1). The interrupts can be globally or individually enabled or disabled.
The master can receive multiple interrupt requests at once. It can also receive a request while the
core is already processing another interrupt. The master uses a programmable priority structure
that determines:
• The order in which to process multiple interrupt requests
• Which requests can interrupt the processing of other requests
When the master receives an interrupt request, it checks to see that the interrupt is enabled and
determines its priority. If the interrupt is enabled and has sufficient priority, the master sends the
request to the core. This causes the core to initiate an internal interrupt acknowledge cycle.