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3-5
CORE OVERVIEW
3.2.4 Execution Unit
The Execution Unit executes the instructions from the Instruction Queue and therefore commu-
nicates with all other units required to complete the instruction. The functions of its three subunits
are given below.
• The Control Unit contains microcode and special parallel hardware that speeds multiply,
divide, and effective address calculation.
• The Data Unit contains the (Arithmetic Logic Unit) ALU, a file of eight 32-bit general-
purpose registers, and a 64-bit barrel shifter (which performs multiple bit shifts in one
clock). The Data Unit performs data operations requested by the Control Unit.
• The Protection Test Unit checks for segmentation violations under the control of the
microcode.
To speed the execution of memory reference instructions, the Execution Unit partially overlaps
the execution of any memory reference instruction with the previous instruction.
3.2.5 Segmentation Unit
The Segmentation Unit translates logical addresses into linear addresses at the request of the Ex-
ecution Unit. The on-chip Segment Descriptor Cache stores the currently used segment descrip-
tors to speed this translation. At the same time it performs the translation, the Segmentation Unit
checks for bus-cycle segmentation violations. (These checks are separate from the static segmen-
tation violation checks performed by the Protection Test Unit.) The translated linear address is
truncated to a 24-bit physical address.
3.2.6 Paging Unit
When the Intel386 CX processor paging mechanism is enabled, the Paging Unit translates linear
addresses generated by the Segmentation Unit or the Instruction Prefetch Unit into physical ad-
dresses. (When paging is not enabled, the physical address is the same as the linear address, and
no translation is necessary.) The Page Descriptor Cache stores recently used Page Directory and
Page Table entries in its Translation Lookaside Buffer (TLB) to speed this translation. The Paging
Unit forwards physical addresses to the Core Bus Unit to perform memory and I/O accesses.