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7-1
CHAPTER 7
SYSTEM MANAGEMENT MODE
The Intel386™ EX processor provides a mechanism for system management with a combination
of hardware and CPU microcode enhancements. For low power systems, the primary function of
SMM is to provide a transparent means for power management. For systems where power man-
agement is not critical, SMM may be used for other functions such as alternate operating systems,
debuggers, hard disk drive backup, or virtual I/O.
This chapter is organized as follows:
• System Management Mode Overview (see below)
• SMM Hardware Interface (page 7-1)
• System Management Mode Programming and Configuration (page 7-3)
• The Intel386 EX Processor Identifier Registers (page 7-15)
• Programming Considerations (page 7-16)
7.1 SYSTEM MANAGEMENT MODE OVERVIEW
An externally generated system management interrupt (SMI#) allows the execution of system-
wide routines that are independent and transparent to the operating system. The system manage-
ment mode (SMM) architectural extensions to the Intel386 CPU consist of the following ele-
ments:
• An interrupt input pin (SMI#) to invoke SMM
• An output pin (SMIACT#) to identify execution state
• A new instruction (RSM, executable only from SMM) to exit SMM
7.2 SMM HARDWARE INTERFACE
The Intel386 EX processor provides two pins for use in SMM systems: SMI# and SMIACT#.
7.2.1 System Management Interrupt Input (SMI#)
The SMI# input signal is used to invoke system management mode. SMI# is a falling edge
triggered interrupt input signal and is the highest priority of all external interrupt sources. SMI#
forces the core into SMM at the completion of the current instruction. SMI# has these
characteristics:
• SMI# is not maskable.
• SMI# is recognized on an instruction boundary and at each iteration for repeat string
instructions.
• SMI# does not break locked bus cycles.