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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-26
6.3.5 Halt/Shutdown Cycle
The halt condition occurs in response to a HALT instruction. The shutdown condition occurs
when the processor is processing a double fault and encounters a protection fault; the processor
cannot recover and therefore, shuts down. Externally, a shutdown cycle differs from a halt cycle
only in the resulting address bus outputs. The sequence of signals for a halt cycle is as follows:
1. As with other bus cycles, a halt or shutdown cycle is initiated by driving the address and
status signals active and asserting ADS#. Figure 6-10 shows a halt bus cycle. The address
and status signals are driven to the following active states:
• M/IO# and W/R# are driven high and D/C# is driven low to indicate a halt cycle or a
shutdown cycle.
• The address bus outputs a byte address of 2 for a halt condition and a byte address of
0 for a shutdown condition. These signals are used by external devices to respond to
the halt or shutdown cycle.
NOTE
The halt or shutdown bus cycle appears as a memory write operation to byte
address 0 or 2 (depending on whether a shutdown or halt cycle is being
performed) if the D/C# signal is not decoded. External address decoders need
to decode the D/C# signal to avoid erroneous writes to devices in this address
region; otherwise, a halt or shutdown cycle corrupts the data at those
addresses. RD#, WR# and the chip-select signals, UCS# and CS6:0#, are
inactive during halt cycles.
2. READY# can be generated externally or internally to terminate a Halt/Shutdown cycle.
The HSREADY bit in the Power Control Register (PWRCON, see Figure 8-5 in Chapter
8), can be set to generate an internal READY# for halt/shutdown cycles. If internal
READY# generation is enabled, then the LBA# signal goes active and behaves as
described in “Ready Logic” on page 6-10. Also, the cycle is always a zero-wait-state
cycle. When external READY# is required to terminate the halt/shutdown cycle, then
READY# may be delayed to add wait-states. The processor remains in the halt or
shutdown condition until one of the following occurs:
• NMI goes active; the processor then services the interrupt.
• RESET goes active; the processor is reinitialized.
• In the halt condition (but not in the shutdown condition), if maskable interrupts are
enabled, an active INTR input causes the processor to end the halt cycle and service
the interrupt. The processor can service processor extension (PEREQ) requests and
hold (HOLD) requests while in the halt or shutdown condition.
• The processor is in the halt condition and SMI# goes active; the processor then
services the SMI#. When the processor is in the shutdown condition, SMI# has no
effect.