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6-19
BUS INTERFACE UNIT
6.3.3 Pipelined Cycle
The pipelining feature of the processor is normally used to achieve zero-wait-state memory sub-
systems using devices that are slower than those in a zero-wait-state non-pipelined system. Pipe-
lining allows bus cycles to be overlapped, increasing the amount of time available for the memory
or I/O device to respond. The next address (NA#) input controls pipelining. NA# is generated by
logic in the system to indicate that the address and status buses are no longer needed by the sys-
tem. When pipelining is not desired in a system, the NA# input should be tied inactive.
During any particular bus cycle, NA# is sampled only after the address and status have been valid
for one T-state (the T1P state of pipelined cycles or the first T2 state of nonpipelined cycles) and
is continuously sampled in each subsequent T-state until it is found active or the bus cycle is ter-
minated. In particular, NA# is sampled at the rising CLK2 edge in the middle of the T-state (rising
edge of Phase 2).
When the system is designed to assert NA#, pipelining may be dynamically requested on a cycle-
by-cycle basis by asserting NA#. Typically, only some devices in a system are pipelined.
NOTE
Asserting the NA# pin is a request for pipelining. Asserting NA# during a bus
cycle does not guarantee that the next cycle is pipelined. NA# is ignored
during I/O cycles and must be kept deasserted during the T2 states of BS8
memory cycles.
During the T2 state of a nonpipelined cycle, if NA# is sampled active, one of four states occur:
• If a bus cycle is internally pending in the processor and READY# is returned inactive to the
processor and the HOLD input is inactive, then the address, byte enables, and bus status
signals for the next bus cycle are driven and the processor bus unit enters a T2P state. T2P
states are repeated until the bus cycle is terminated.
• If a bus cycle is internally pending in the processor and READY# is returned active to the
processor and the HOLD input is inactive, then the address, byte enables, and bus status
signals for the next bus cycle are driven and the processor bus unit enters a T1
(nonpipelined) state. In effect, the NA# input is ignored in this case.
• If READY# is returned inactive and either a bus cycle is not internally pending or the
HOLD input is active, then the address and byte enables enter an unknown state, the bus
status signals go inactive, and the processor bus unit enters a T2i state. If the bus cycle is not
terminated, then the next state is either a T2P state or a T2i state depending on whether a
bus cycle is pending.
• If HOLD is asserted to the processor and READY# is returned active, then the Th state is
entered from a T2 state regardless of whether an internal bus cycle is pending.
Figure 6-8 illustrates the effect of NA# (Figure 6-7 shows the full bus state diagram including the
states related to pipelining). During the second T-state (T2) of a nonpipelined read cycle (cycle
2), NA# is sampled low. A bus cycle was pending internally (cycle 3) and the address, byte en-
ables, and bus status signals for this pending bus cycle (cycle 3) are driven during the next T2P
state (the first wait state of the current bus cycle). The RD# and WR# signals do not change until
READY# is sampled low.