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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
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6.4 BUS LOCK
In a system in which more than one device (a bus master) may control the local bus, locked cycles
are used to make sequential bus cycles indivisible. Otherwise, the cycles may be separated by a
cycle from another bus master.
Any bus cycles that must be performed back-to-back, without any intervening bus cycles by other
bus masters, must be locked. The use of a semaphore is one example of this concept. The value
of a semaphore indicates a condition such as the availability of a device. If the CPU reads a sema-
phore to determine that a device is available, then writes a new value to the semaphore to indicate
that it intends to take control of the device, the read cycle and write cycle should be locked to
prevent another bus master from reading from or writing to the semaphore in between the two
cycles.
The LOCK# output indicates, to the other bus masters, that they may not gain control of the bus.
In addition, when LOCK# is asserted, the processor does not recognize a HOLD request from an-
other bus master.
6.4.1 Locked Cycle Activators
The LOCK# signal is activated explicitly by the LOCK prefix on certain instructions. (The in-
structions are listed in the Intel386™ SX Microprocessor Programmer’s Reference Manual, order
number 240331). LOCK# is also asserted automatically for XCHG instructions, descriptor up-
dates, and interrupt acknowledge cycles.
6.4.2 Locked Cycle Timing
LOCK# is activated on the CLK2 edge that begins the first locked bus cycle and deactivated when
READY# is sampled active at the end of the last bus cycle to be locked. LOCK# is activated and
deactivated on these CLK2 edges regardless of address pipelining. If address pipelining is used,
LOCK# remains active until the current bus cycle is completed (READY# sampled active for the
current bus cycle). Consequently, the LOCK# signal can extend into the next memory access cy-
cle that does not need to be locked. (See Figure 6-14). The result is that the use of the bus by an-
other bus master is delayed by one bus cycle.